The prior art in path-delay testing dates to 1985, with the definition of a delay model based on path delay faults. This initial paper and several other papers that followed it taught algorithms to generate tests for path-delay faults in combinational logic circuits. Due to the fact that nobody actually produces purely combinational circuits any more, the only way for these algorithms to be applied to a real circuit is essentially to double each memory device in the circuit so that it can store the two patterns (first clock cycle pattern and second clock cycle pattern) required for the path-delay test as completely independent patterns. This would roughly double the size of the memory portion of the circuit (the section 12 of FIG. 1), which no price-competitive manufacturer is willing to do. As a consequence, all these prior combinational logic approaches to path-delay testing remain largely academic exercises which cannot be used in modern integrated circuit design.
Test generation methods that could be applied to path-delay faults in standard scan sequential circuits first began to appear in 1991. These methods were the first to make feasible the path-delay testing of real circuits. Unfortunately, the methods described in all known papers/publications/patents that target standard scan sequential circuits used a simplified logic algebra that did not include hazard-free values. Hazard-free being a logic value that is to remain at the same logic level and is free of a timing glitch. As a consequence, the methods are unable to target robust tests, which means that any tests they generate may be invalidated by timing problems in other parts of the circuit. In other words, by not using hazard-free values a time delay fault may be inaccurately detected when a time delay fault really didn't occur or vice versa, an actual time delay fault could go unreported due to a static timing hazard. A recent testing method claims to be able to generate robust tests for general sequential circuitry, including standard scan sequential circuits. The absence of certain necessary logic values, however, means that this algorithm is defective and may declare a path untestable even when a robust test exists. None of the prior art provides an error-free method for generating robust tests for standard scan sequential circuitry.